When making an integrated circuit (which may also be referred to as an IC, chip or device), a design layout of the IC is made using, for example, CAD tools. A reticle or mask is then produced for the IC design layout and then photolithography is used to transfer features from the reticle or mask to a die (integrated circuit semiconductor wafer).
Various techniques are used to reduce the level of defects in the resultant die. For instance, prior to the production of the reticle, the design layout may be optimized using optical proximity correction (OPC) to create a reticle layout. This optimization process amends the physical design layout in order to avoid optical or process distortions also known as patterning defects when features are transferred from the reticle or mask that may cause failures of the device. The OPC optimization process discretizes the design layout into moveable segments and adds control points to the design where it is determined that patterning defects may occur. The segmented features of the IC design are then amended using a model of the patterning process to calculate patterning error information at these control points until it is determined that the patterning defects are fixed. Once the patterning defects are fixed there is no further use for the control points.
Once the reticle is produced and wafer dies have been manufactured, features on these wafer dies may be measured or micrographed by scanning electron microscope (SEM) techniques to evaluate if there are patterning defects which were not adequately fixed during OPC. Obviously, individually measuring or micrographing each feature on a multi-million gate device is unfeasible. Therefore, certain representative features are chosen. These representative features can be determined by rule-based guidelines or by lithographic simulation predictions.
Where wafer patterning defects are found that would result in an unacceptable failure rate for the IC, the reticle layout must be adjusted to avoid these critical defects. This results in further iterations of OPC, build and test of the die until no critical defects are found or the die meets other success criteria. This is a costly and labor intensive process and may result in many time consuming iterations until a successful reticle layout is found.